library IEEE;
use IEEE.std_logic_1164.ALL;

use std.env.finish;

entity tb_x4 is
end entity;

architecture sim of tb_x4 is
	signal fastclk : std_logic := '0';
	signal slowclk : std_logic;
	signal out_strobe : std_logic;
	signal outclk : std_logic;
	signal locked : std_logic;
begin
	-- fast clock (100 MHz)
	fastclk <= not fastclk after 5 ns;	-- 10 ns period

	-- stimuli
	process
	begin
		slowclk <= '0';
		-- test normal operation with 2 MHz input
		for i in 0 to 20 loop
			wait for 250 ns;
			slowclk <= not slowclk;
		end loop;

		assert locked = '1' severity error;

		slowclk <= 'U';
		wait for 100 ns;		-- let the error propagate

		slowclk <= '0';

		-- test normal operation with 200 kHz input
		for i in 0 to 20 loop
			wait for 2500 ns;
			slowclk <= not slowclk;
		end loop;

		assert locked = '1' severity error;

		finish;
	end process;

	-- UUT
	uut : entity work.x4
		port map(
			fastclk => fastclk,
			slowclk => slowclk,
			out_strobe => out_strobe,
			locked => locked
		);

	outclk <= '0' when locked = '0' else
		not outclk when rising_edge(fastclk) and out_strobe = '1';
end architecture;